Semiconductor device manufacturing method and substrate processing system

ABSTRACT

A semiconductor device manufacturing method includes: forming an etching mask having a predetermined circuit pattern on a surface of an etching target film disposed on a semiconductor substrate; etching the etching target film through the etching mask to form a groove or hole in the etching target film; removing the etching mask by a process including at least a process using an ozone-containing gas; and recovering damage of the etching target film caused before or in said removing the etching mask, while supplying a predetermined recovery gas.

CROSS REFERENCE TO RELATED APPLICATION

The present divisional application claims the benefit of priority under35 U.S.C. 120 to application Ser. No. 11/564,548, filed Nov. 29, 2006,and claims the benefit of priority under 35 U.S.C. 119 from JapaneseApplication No. 2005-346854, filed on Nov. 30, 2005. The entire contentsof application Ser. No. 11/564,548 are hereby incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of manufacturing asemiconductor device by use of, e.g., a single damascene method or dualdamascene method, and a substrate processing system used formanufacturing a semiconductor device.

2. Description of the Related Art

In semiconductor device manufacturing processes, a dual damascene methodis frequently used for forming interconnection lines embedded intrenches and/or connection holes (for example, see Jpn. Pat. Appln.KOKAI Publication No. 2002-83869). FIGS. 1A to 1I are explanatory viewsschematically showing a method of forming a Cu interconnection line,using a conventional dual damascene method.

At first, for example, an interconnection layer 500, an inter-levelinsulating film 501, and an anti-reflective coating 502 are formed inthis order on a substrate. Further, a first resist film 503 is formed onthe surface of the multi-layer structure thus formed (FIG. 1A). Then,patterning of the first resist film 503 is performed by aphotolithography technique to form a predetermined pattern (FIG. 1B). Inthis patterning step, the first resist film 503 is subjected to lightexposure with a predetermined pattern, and the light-exposed portion isselectively removed by development. Subsequently, the anti-reflectivecoating 502 and inter-level insulating film 501 are etched by an etchingprocess using the first resist film 503 as a mask. Consequently, aconnection hole 504 is formed to extend from the surface of themulti-layer structure to the interconnection layer 500 (FIG. 1C).

Thereafter, for example, the first resist film 503, which is notnecessary any more, is peeled and removed by an ashing process (FIG.1D). Then, a new second resist film 505 for forming an interconnectiongroove is formed (FIG. 1E). Then, patterning of the second resist film505 is performed by a photolithography technique (FIG. 1F). Then, theanti-reflective coating 502 and a part of the inter-level insulatingfilm 501 are etched by an etching process using the second resist film505 as a mask. Consequently, an interconnection groove 506 is formed tobe connected to the connection hole 504 and wider than the connectionhole 504 (FIG. 1G). Then, the second resist film 505, which is notnecessary any more, is peeled and removed (FIG. 1H). Then, theconnection hole 504 and interconnection groove 506 are filled with Cumaterial, so that a Cu interconnection line 507 is formed (FIG. 1I).

Incidentally, with a decrease in size of semiconductor devices, theparasitic capacitance of inter-level insulating films has become animportant factor to improve the performance of interconnection lines.For this purpose, low dielectric constant materials (Low-k materials)are used as the material of inter-level insulating films. In general,materials including alkyl groups, such as methyl groups, as end groupsare used as low dielectric constant materials (Low-k materials) forforming inter-level insulating films.

However, according to the conventional damascene process describedabove, when a resist film is peeled, the inter-level insulating film 501made of a Low-k material is damaged. This damage increases thedielectric constant of the inter-level insulating film 501, anddeteriorates some effects obtained by using the Low-k material.

In order to minimize such damage as far as possible, it has beenproposed to perform high temperature ashing by use of He gas and H₂ gasfor resist peeling, by A. Matsushita et al. “Low damage ashing usingH₂/He plasma for porous ultra Low-k”, Proceeding IITC 2003 pp 147-149.However, this technique is insufficient not only in the effect ofsuppressing damage but also in the effect of peeling resist, and thus isunpractical.

BRIEF SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor devicemanufacturing method to manufacture a semiconductor device excellent inelectrical characteristics and reliability, and a substrate processingsystem to realize a manufacturing method of this kind.

Another object of the present invention is to provide a computerreadable memory medium that stores a control program to execute amanufacturing method of this kind.

According to a first aspect of the present invention, there is provideda semiconductor device manufacturing method comprising: forming anetching mask having a predetermined circuit pattern on a surface of anetching target film disposed on a semiconductor substrate; etching theetching target film through the etching mask to form a groove or hole inthe etching target film; removing the etching mask by a processincluding at least a process using an ozone-containing gas; andrecovering damage of the etching target film caused before or in saidremoving the etching mask, while supplying a predetermined recovery gas.

In the manufacturing method according to the first aspect, said removingthe etching mask may be performed by denaturing the etching mask byozone and water vapor used as the process gas, and then processing theetching mask by purified water or a chemical liquid. Alternatively, saidremoving the etching mask may be performed by denaturing the etchingmask by ozone used as the process gas, and then processing the etchingmask by purified water or a chemical liquid.

The method may further comprise cleaning the semiconductor substrateafter said removing the etching mask and before said recovering damage.Further, said recovering damage may be performed by a silylation processusing a silylation gas as the recovery gas.

According to a second aspect of the present invention, there is provideda semiconductor device manufacturing method comprising: forming anetching mask having a predetermined circuit pattern on a surface of anetching target film disposed on a semiconductor substrate; etching theetching target film through the etching mask to form a groove or hole inthe etching target film; removing the etching mask; and recoveringdamage of the etching target film caused before or in said removing theetching mask, while supplying a predetermined recovery gas, wherein saidrecovering damage comprises heating the semiconductor substrate beforeand/or after starting supply of the recovery gas.

In the manufacturing method according to the second aspect, saidrecovering damage may be performed by a silylation process using asilylation gas as the recovery gas. In this case, a temperature of 50 to200° C. is preferably used for said heating before and/or after startingsupply of the recovery gas. Further, said heating preferably comprisesheating before and after starting supply of the recovery gas, such thata first temperature is used for said heating before starting supply ofthe recovery gas, and a second temperature higher than the firsttemperature is used for said heating after starting supply of therecovery gas.

According to a third aspect of the present invention, there is provideda semiconductor device manufacturing method comprising: forming anetching mask having a predetermined circuit pattern on a surface of anetching target film disposed on a semiconductor substrate; etching theetching target film by dry etching through the etching mask to form agroove or hole in the etching target film; removing the etching mask bya dry process subsequently to said etching; supplying moisture into aspace accommodating the semiconductor substrate to apply moisture ontothe semiconductor substrate after said removing the etching mask;heating the semiconductor substrate with moisture adsorbed thereon; andrecovering damage of the etching target film caused before or in saidremoving the etching mask, while supplying a predetermined recovery gasafter said heating.

In the manufacturing method according to the third aspect, said etchingby dry etching to form a groove or hole in the etching target film, saidremoving the etching mask, and said recovering damage may be performedin one unit.

Said removing the etching mask may be performed by a dry ashing processusing oxygen plasma. Alternatively, said removing the etching mask maybe performed by a dry process using oxygen radicals.

Said recovering damage may comprise heating the substrate after startingsupply of the recovery gas. In this case, it is preferable that a firsttemperature is used for said heating the semiconductor substrate withmoisture adsorbed thereon, and a second temperature higher than thefirst temperature is used for said heating after starting supply of therecovery gas.

Said recovering damage may be performed by a silylation process using asilylation gas as the recovery gas. In this case, a temperature of 50 to200° C. is preferably used for heating the semiconductor substratebefore starting supply of the silylation gas used as the recovery gas.Further, said applying moisture onto the semiconductor substrate may beperformed by supplying atmospheric gas into the space accommodating thesemiconductor substrate.

In the manufacturing method according to each of the first to thirdaspects, where a silylation process is performed as the recoveryprocess, the silylation process is preferably performed while using acompound including silazane bonds (Si—N) in molecules as the recoverygas. The compound including silazane bonds in molecules is preferablyselected from TMDS (1,1,3,3-Tetramethyldisilazane), TMSDMA(Dimethylaminotrimethylsilane), DMSDMA (Dimethylsilyldimethylamine),TMSPyrole (1-Trimethylsilylpyrole), BSTFA(N,O-Bis(trimethylsilyl)trifluoroacetamide), and BDMADMS(Bis(dimethylamino)dimethylsilane).

According to a fourth aspect of the present invention, there is provideda substrate processing system for processing a semiconductor substrateafter using an etching apparatus to etch an etching target layerdisposed on the semiconductor substrate through an etching mask having apredetermined pattern so as to form a groove or hole in the etchingtarget film, the system comprising: an apparatus configured to denaturethe etching mask by a process gas containing ozone; a cleaning apparatusconfigured to remove the denatured etching mask by purified water or achemical liquid; a recovering apparatus configured to perform a recoveryprocess while supplying a predetermined recovery gas, to recover damageof the etching target film; and a control section configured to controlthe apparatuses, wherein the control section carries out control suchthat, after the etching mask is removed, the semiconductor substrate istransferred into the recovering apparatus, in which the recovery processis performed.

In the system according to the fourth aspect, the apparatus configuredto denature the etching mask by a process gas containing ozone may useozone and water vapor or ozone alone as the process gas.

The apparatus configured to denature the etching mask, the cleaningapparatus, and the recovering apparatus may be arranged in the sameunit.

The control section may control the recovering apparatus to heat thesemiconductor substrate before and/or after starting supply of therecovery gas. Further, the control section may carry out control to heatthe semiconductor substrate at a first temperature before startingsupply of the recovery gas, and to heat the semiconductor substrate at asecond temperature higher than the first temperature after startingsupply of the recovery gas, in the recovering apparatus.

The recovering apparatus may be configured to perform a silylationprocess using a silylation gas as the recovery gas. In this case, thecontrol section preferably carries out control to use a temperature of50 to 200° C. for said heating before and/or after starting supply ofthe recovery gas.

According to a fifth aspect of the present invention, there is provideda substrate processing system comprising: a dry etching apparatusconfigured to etch an etching target layer disposed on a semiconductorsubstrate by dry etching through an etching mask having a predeterminedpattern so as to form a groove or hole in the etching target film; a dryashing apparatus configured to remove the etching mask by dry ashing; arecovering apparatus configured to perform a recovery process forrecovering damage of the etching target film, while supplying apredetermined recovery gas; a heating mechanism configured to heat thesemiconductor substrate; a mechanism configured to apply moisture ontothe semiconductor substrate; and a control section configured to controlthe apparatuses and the mechanisms, wherein the dry etching apparatus,the dry ashing apparatus, and the recovering apparatus are integratedlyarranged in the same processing unit to perform processes in a vacuumatmosphere, and the control section carries out control such that, afterthe etching mask is removed by the dry ashing apparatus, moisture isapplied onto the semiconductor substrate by the mechanism configured toapply moisture, then the semiconductor substrate is heated by theheating mechanism, and then the recovery process is performed by therecovering apparatus.

In the system according to the fifth aspect, the control section maycarry out control to heat the semiconductor substrate after startingsupply of the recovery gas, in the recovering apparatus. In this case,the control section preferably carries out control to heat thesemiconductor substrate at a first temperature before starting supply ofthe recovery gas, and to heat the semiconductor substrate at a secondtemperature higher than the first temperature after starting supply ofthe recovery gas, in the recovering apparatus.

The recovering apparatus may be configured to perform a silylationprocess using a silylation gas as the recovery gas. In this case, thecontrol section preferably carries out control to heat the semiconductorsubstrate at 50 to 200° C. before starting supply of the silylation gasas the recovery gas.

The control section preferably carries out control to heat thesemiconductor substrate at 50 to 200° C. after starting supply of thesilylation gas as the recovery gas, in the recovering apparatus. In thiscase, the control section preferably carries out control to heat thesemiconductor substrate at a first temperature before starting supply ofthe silylation gas, and to heat the semiconductor substrate at a secondtemperature higher than the first temperature after starting supply ofthe silylation gas, in the recovering apparatus.

The mechanism configured to apply moisture onto the semiconductorsubstrate may comprise an atmospheric gas supply portion disposed in theprocessing unit.

According to a sixth aspect of the present invention, there is provideda computer readable memory medium that stores a control program forexecution on a computer to control a substrate processing system forprocessing a substrate, wherein the control program, when executed,causes the computer to control the substrate processing system toconduct a semiconductor device manufacturing method comprising: formingan etching mask having a predetermined circuit pattern on a surface ofan etching target film disposed on a semiconductor substrate; etchingthe etching target film through the etching mask to form a groove orhole in the etching target film; removing the etching mask by a processincluding at least a process using an ozone-containing gas; andrecovering damage of the etching target film caused before or in saidremoving the etching mask, while supplying a predetermined recovery gas.

According to a seventh aspect of the present invention, there isprovided a computer readable memory medium that stores a control programfor execution on a computer to control a substrate processing system forprocessing a substrate, wherein the control program, when executed,causes the computer to control the substrate processing system toconduct a semiconductor device manufacturing method comprising: formingan etching mask having a predetermined circuit pattern on a surface ofan etching target film disposed on a semiconductor substrate; etchingthe etching target film through the etching mask to form a groove orhole in the etching target film; removing the etching mask; andrecovering damage of the etching target film caused before or in saidremoving the etching mask, while supplying a predetermined recovery gas,wherein said recovering damage comprises heating the semiconductorsubstrate before and/or after starting supply of the recovery gas.

According to an eighth aspect of the present invention, there isprovided a computer readable memory medium that stores a control programfor execution on a computer to control a substrate processing system forprocessing a substrate, wherein the control program, when executed,causes the computer to control the substrate processing system toconduct a semiconductor device manufacturing method comprising: formingan etching mask having a predetermined circuit pattern on a surface ofan etching target film disposed on a semiconductor substrate; etchingthe etching target film by dry etching through the etching mask to forma groove or hole in the etching target film; removing the etching maskby a dry process subsequently to said etching; supplying moisture into aspace accommodating the semiconductor substrate to apply moisture ontothe semiconductor substrate after said removing the etching mask;heating the semiconductor substrate with moisture adsorbed thereon; andrecovering damage of the etching target film caused before or in saidremoving the etching mask, while supplying a predetermined recovery gasafter said heating.

According to the present invention, a method may be performed, asfollows. Specifically, an etching target film disposed on asemiconductor substrate is etched through an etching mask to form aninterconnection groove or connection hole. Then, the etching mask isremoved by a process including a process using a process gas containingozone. Specifically, at this time, the etching mask is denatured byozone and water vapor used as a process gas, and then is processed bypurified water or a chemical liquid. Alternatively, the etching mask isdenatured by ozone used as a process gas, and then is processed bypurified water or a chemical liquid. Thereafter, a recovery processusing a process gas is performed by, e.g., a silylation process.Consequently, the etching mask can be removed at a practical rate, andthen the damage of the etching target film caused in removing theetching mask can be sufficiently recovered. It follows that asemiconductor device can be manufactured to have improved electricalcharacteristics and reliability.

Further, according to the present invention, a method may be performed,as follows. Specifically, an etching target film disposed on asemiconductor substrate is etched through an etching mask to form aninterconnection groove or connection hole. Then, the etching mask isremoved, and then a recovery process using a recovery gas is performedby, e.g., a silylation process. At this time, the semiconductorsubstrate is heated before and/or after starting supply of the recoverygas. Consequently, the effect of the recovery process is enhanced, sothat the damage of the etching target film caused in removing theetching mask can be sufficiently recovered. It follows that asemiconductor device can be manufactured to have improved electricalcharacteristics and reliability.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIGS. 1A to 1I are sectional views showing steps of a semiconductordevice manufacturing process using a conventional dual damascene method;

FIG. 2 is an explanatory view schematically showing the arrangement of asemiconductor device manufacturing system used for a semiconductordevice manufacturing process according to a first embodiment of thepresent invention;

FIG. 3 is a plan view schematically showing the structure of adenaturing/cleaning/recovering apparatus used in the semiconductordevice manufacturing system shown in FIG. 2;

FIG. 4 is a front view schematically showing the structure of thedenaturing/cleaning/recovering apparatus shown in FIG. 3;

FIG. 5 is a back view schematically showing the structure of thedenaturing/cleaning/recovering apparatus shown in FIG. 3;

FIG. 6 is a sectional view schematically showing a denaturing unitdisposed in the denaturing/cleaning/recovering apparatus;

FIG. 7 is a sectional view schematically showing a silylation unitdisposed in the denaturing/cleaning/recovering apparatus;

FIG. 8 is a sectional view schematically showing a cleaning unitdisposed in the denaturing/cleaning/recovering apparatus;

FIG. 9 is a flowchart showing a semiconductor device manufacturingprocess employing a single damascene method, performed by thesemiconductor device manufacturing system shown in FIG. 2;

FIGS. 10A to 10H are sectional views showing steps of the flow shown inFIG. 9;

FIG. 11 is a view for explaining damage of a Low-k film and a recoverymechanism thereof by silylation;

FIG. 12 is a flowchart showing a semiconductor device manufacturingprocess employing a dual damascene method, performed by thesemiconductor device manufacturing system shown in FIG. 2;

FIGS. 13A to 13K are sectional views showing steps of the flow shown inFIG. 12;

FIGS. 14A to 14C are sectional views showing samples used for confirmingeffects of the first embodiment;

FIG. 15 is an explanatory view schematically showing the arrangement ofa semiconductor device manufacturing system used for a semiconductordevice manufacturing process according to a second embodiment of thepresent invention;

FIG. 16 is a plan view schematically showing the structure of anetching/ashing/recovering apparatus used in the semiconductor devicemanufacturing system shown in FIG. 15;

FIG. 17 is a sectional view schematically showing an ashing unitdisposed in the etching/ashing/recovering apparatus;

FIG. 18 is a sectional view schematically showing a silylation unitdisposed in the etching/ashing/recovering apparatus;

FIG. 19 is a flowchart showing a semiconductor device manufacturingprocess employing a single damascene method, performed by thesemiconductor device manufacturing system shown in FIG. 15;

FIGS. 20A to 20G are sectional views showing steps of the flow shown inFIG. 19; and

FIGS. 21A to 21C are views for explaining a method in which a silylationprocess is arranged to sequentially perform preheating and heating afterstarting supply of a silylation agent.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will now be described withreference to the accompanying drawings. Hereinafter, the presentinvention is exemplified by a case where a semiconductor device ismanufactured by a single damascene method and a case where asemiconductor device is manufactured by a dual damascene method.

FIG. 2 is an explanatory view schematically showing the arrangement of asemiconductor device manufacturing system used for a semiconductordevice manufacturing process according to a first embodiment of thepresent invention. This semiconductor device manufacturing systemincludes a process section 100 and a main control section 110. Theprocess section 100 includes an SOD (Spin On Dielectric) apparatus 101,a resist coating/development apparatus 102, a light exposure apparatus103, a denaturing/cleaning/recovering apparatus 104 for performingresist denaturing, cleaning, and recovery processes, an etchingapparatus 105, a sputtering apparatus 106 used as a PVD apparatus, anelectrolytic plating apparatus 107, and a CMP apparatus 109 used as apolishing apparatus. The main control section 110 includes a processcontroller 111, a user interface 112, and a memory portion 113. The SODapparatus 101, sputtering apparatus 106, and electrolytic platingapparatus 107 of the process section 100 are film formation apparatuses.As a method for transferring a wafer W between apparatuses in theprocess section 100, a transfer method by an operator and/or a transfermethod by a transfer unit (not shown) are used.

Each of the apparatuses in the process section 100 is connected to andcontrolled by the process controller 111 having a CPU. The processcontroller 111 is connected to the user interface 112, which includes,e.g., a keyboard and a display, wherein the keyboard is used for aprocess operator to input commands for operating the apparatuses in theprocess section 100, and the display is used for showing visualizedimages of the operational status of the apparatuses in the processsection 100. Further, the process controller 111 is connected to thememory portion 113, which stores recipes with control programs andprocess condition data recorded therein, for realizing various processesperformed in the process section 100 under the control of the processcontroller 111.

A required recipe is retrieved from the memory portion 113 and executedby the process controller 111 in accordance with an instruction or thelike input through the user interface 112. Consequently, each of variouspredetermined processes is performed in the process section 100 underthe control of the process controller 111. Recipes may be stored in areadable memory medium, such as a CD-ROM, hard disk, flexible disk, ornonvolatile memory. Further, recipes may be utilized on-line, while itis transmitted among the respective apparatuses in the process section100, or transmitted from an external apparatus through, e.g., adedicated line, as needed.

The main control section 110 may be arranged to control all theapparatuses, or may be arranged to perform only global control, whileeach of the apparatuses or each predetermined set of apparatuses isprovided with and controlled by its own subordinate control section.

The SOD apparatus 101 is used to apply a chemical liquid onto a wafer Wto form an inter-level insulating film formed of, e.g., a Low-k film, oran etching stopper film by a spin coating method. Although the structureof the SOD apparatus 101 is not shown in detail, the SOD apparatus 101includes a spin coater unit and a heat processing unit to perform a heatprocess on a wafer W with a coating film formed thereon. In the case ofa wafer processing system, a CVD apparatus may be used to form aninsulating film on a wafer W by a chemical vapor deposition (CVD)method, in place of the SOD apparatus 101.

The resist coating/development apparatus 102 is used to form a resistfilm used as an etching mask, and an anti-reflective coating. Althoughthe resist coating/development apparatus 102 is not shown in detail, theresist coating/development apparatus 102 includes a resist coating unit,a BARC coating unit, a sacrificial film coating unit, a developing unit,and thermal processing units. The resist coating unit is arranged toapply a resist liquid onto a wafer W to form a resist film by spincoating. The BARC coating unit is arranged to apply an anti-reflectivecoating (BARC) onto a wafer W. The sacrificial film coating unit isarranged to apply a sacrificial film onto a wafer W. The developing unitis arranged to perform a development process on a resist film which hasbeen subjected to light exposure with a predetermined pattern in thelight exposure apparatus 103. The thermal processing units are arrangedto respectively perform thermal processes on a wafer W with a resistfilm formed thereon, a wafer W treated by a light exposure process, anda wafer W treated by a development process. The light exposure apparatus103 is used to subject a wafer W with a resist film formed thereon tolight exposure with a predetermined circuit pattern.

As described later in detail, the denaturing/cleaning/recoveringapparatus 104 is arranged to perform a denaturing process of a resistfilm or the like after an etching process, a cleaning and removingprocess of the resist film or the like, using purified water or achemical liquid, after the denaturing process, and a recovery process ofan inter-level insulating film for damage caused in removing the resistfilm.

The etching apparatus 105 is arranged to perform an etching process onan inter-level insulating film or the like formed on a wafer W. Theetching process may be of a type using plasma or a type using a chemicalliquid.

The sputtering apparatus 106 is used to form, e.g., each of ananti-diffusion film and a Cu seed layer. The electrolytic platingapparatus 107 is arranged to embed Cu in a groove having a Cu seed layerformed therein to form a groove interconnection line. The CMP apparatus109 is arranged to perform a planarization process on a surface of agroove interconnection line filled with Cu, and so forth.

Next, a detailed explanation will be given of thedenaturing/cleaning/recovering apparatus 104 which plays an importantpart of this embodiment. FIGS. 3, 4, and 5 are a plan view, a frontview, and a back view, respectively, schematically showing thedenaturing/cleaning/recovering apparatus 104. Thedenaturing/cleaning/recovering apparatus 104 includes a carrier station4, a process station 2, a transfer station 3, and a chemical station 5.The carrier station 4 is arranged such that carriers each storing wafersW are sequentially transferred from other processing apparatuses ontothe carrier station 4. The carrier station 4 is also arranged such thatcarriers each storing wafers W processed in thedenaturing/cleaning/recovering apparatus 104 are transferred from thecarrier station 4 to processing apparatuses for subsequent processes.The process station 2 includes a plurality of processing units arrangedto respectively perform a cleaning process, a denaturing process, and arecovery process. The transfer station 3 is arranged to transfer a waferW between the process station 2 and carrier station 4. The chemicalstation 5 is arranged to perform manufacture, preparation, and storageof a chemical liquid, purified water, gas, and so forth to be used inthe process station 2. The denaturing/cleaning/recovering apparatus 104further includes a control section 26 for controlling the respectivecomponents thereof.

Each carrier C contains therein wafers W essentially in a horizontalstate at regular intervals in the vertical direction (Z-direction). Thewafers W are transferred to and from the carrier C through one side ofthe carrier C, which is opened/closed by a lid 10 a (which is not shownin FIG. 3, but shown in FIGS. 4 and 5 in a detached state).

As shown in FIG. 3, the carrier station 4 has a table 6 on whichcarriers C can be placed at three positions arrayed in a Y-directiondefined in FIG. 3. Each carrier C is placed on the table 6 such that theside provided with the lid 10 a faces a partition wall 8 a between thecarrier station 4 and transfer station 3. The partition wall 8 a haswindow portions 9 a formed therein at positions corresponding to themount positions for carriers C. Each of the window portions 9 a isprovided with a shutter 10 on the transfer station 3 side to open/closethe window portion 9 a. This shutter 10 includes holding means (notshown) for holding the lid 10 a of a carrier C, so that the holdingmeans can hold the lid 11 a and withdraw it into the transfer station 3,as shown in FIGS. 4 and 5.

The transfer station 3 is provided with a wafer transfer unit 7 disposedtherein, which has a wafer transfer pick 7 a for holding a wafer W. Thewafer transfer unit 7 is movable in the Y-direction along guides 7 b(see FIGS. 4 and 5) extending on the floor of the transfer station 3 inthe Y-direction. The wafer transfer pick 7 a is slidable in anX-direction, movable up and down in the Z-direction, and rotatable inthe X-Y plane (θ rotation).

With the arrangement described above, the wafer transfer pick 7 a canaccess any one of the carriers C placed on the table 6, in a state wherethe shutters 10 are retreated to allow the interior of the carriers C tocommunicate with the transfer station 3 through the window portions 9 a.Accordingly, the wafer transfer pick 7 a can transfer a wafer W from anyheight position in each of the carriers C, and can transfer a wafer Wonto any height position in each of the carriers C.

The process station 2 includes two wafer mount units (TRS) 13 a and 13 bon the transfer station 3 side. For example, the wafer mount unit (TRS)13 b is used to place a wafer W when the wafer W is transferred from thetransfer station 3 to the process station 2. The wafer mount unit (TRS)13 a is used to place a wafer W when the wafer W is returned to thetransfer station 3 after it is subjected to a predetermined process inthe process station 2.

On the rear side of the process station 2, there are denaturing units(VOS) 15 a to 15 f arranged to process an anti-reflective coating and/ora resist mask remaining after an etching process, by a process gascontaining ozone (O₃), such as a mixture gas of ozone and water vapor orozone alone, so as to denature them to be soluble in purified water or apredetermined chemical liquid. In the denaturing units (VOS) 15 a to 15f, the resist film used for the etching process only changes thechemical property to be soluble in purified water or a predeterminedchemical liquid, while it maintains the shape.

Silylation units (SCH) 11 a and 11 b are disposed on the denaturingunits (VOS) 15 a and 15 d, and are arranged to perform a silylationprocess as a recovery process to recover damage of an inter-levelinsulating film caused in removing a resist film by the denaturingprocess and cleaning process.

On the front side of the process station 2, there are cleaning units(CNU) 12 a to 12 d arranged to perform a chemical liquid process orwater washing process on a wafer W treated by the denaturing units (VOS)15 a to 15 f, so as to remove a denatured resist film or to perform acleaning process after the removal.

In the process station 2, four hot plate units (HP) 19 a to 19 d arestacked at a position opposite to the wafer mount units (TRS) 13 a and13 b with a main wafer transfer unit 14 interposed therebetween, and arearranged to heat and dry a wafer W treated by the cleaning units (CNU)12 a to 12 d. Further, cooling plate units (COL) 21 a and 21 b arestacked on the wafer mount unit (TRS) 13 a, and are arranged to cool awafer W treated by the heat and dry process. The wafer mount unit (TRS)13 b may be arranged as a cooling plate unit. A fan and filter unit(FFU) 25 is disposed at the top of the process station 2, and isarranged to send clean air into the process station 2.

The main wafer transfer unit 14 is disposed essentially at the center ofthe process station 2, and is arranged to transfer a wafer W within theprocess station 2. The main wafer transfer unit 14 has a wafer transferarm 14 a for transferring a wafer W. The main wafer transfer unit 14 isrotatable about a Z-axis. Further, the wafer transfer arm 14 a ismovable back and forth in a horizontal direction, and movable up anddown in the Z-direction. With this arrangement, the main wafer transferunit 14 can access the respective units disposed in the process station2 to transfer a wafer W between the units, without moving itself in theX-direction.

The chemical station 5 includes a process gas supply portion 16, acleaning liquid supply portion 17, and a silylation agent supply portion18. The process gas supply portion 16 is arranged to supply ozone, watervapor, and so forth as process gases to the denaturing units (VOS) 15 ato 15 f disposed in the process station 2. The cleaning liquid supplyportion 17 is arranged to supply a cleaning liquid to the cleaning units(CNU) 12 a to 12 d. The silylation agent supply portion 18 is arrangedto supply a silylation agent, a carrier gas, and so forth to thesilylation units (SCH) 11 a and 11 b.

Next, a detailed explanation will be given of the structure of thedenaturing unit (VOS) 15 a with reference to the schematic sectionalview shown in FIG. 6. This denaturing unit (VOS) 15 a includes anairtight chamber 30 for accommodating a wafer W. The chamber 30 isformed of a stationary lower container 41 a, and a lid 41 b that coversthe top face of the lower container 41 a. The lid 41 b is movable up anddown by a cylinder 43 fixed to a frame 42 of the film denaturing unit(VOS) 15 a. FIG. 6 shows both of a state where the lid 41 b is in closecontact with the lower container 41 a, and a state where the lid 41 b isretreated above the lower container 41 a.

The lower container 41 a is provided with an O-ring 51 disposed on thetop face of a raised portion at the rim. When the lid 41 b is moved downby the cylinder 43, the rim of the bottom face of the lid 41 b comesinto contact with the top face of the raised portion at the rim of thelower container 41 a and presses the O-ring 51 to form an airtightprocess space in the chamber 30.

The lower container 41 a includes a stage 33 for placing a wafer Wthereon. The stage 33 is provided with proximity pins 44 at a pluralityof positions to support the wafer W.

The stage 33 includes a heater 45 a built therein, and the lid 41 bincludes a heater 45 b built therein, so that each of the stage 33 andlid 41 b is maintained at a predetermined temperature. Consequently, thetemperature of a wafer W can be kept constant.

The lid 41 b has hook members 46 at, e.g., three positions (only two ofthem are shown in FIG. 6) on the bottom face to hold a wafer W. Thewafer W is transferred to and from the hook members 46 by the wafertransfer arm 14 a. When the lid 41 b is moved down while a wafer W issupported by the hook members 46, the wafer W is transferred onto theproximity pins 44 provided on the stage 33, on the way.

The lower container 41 a has a gas feed port 34 a for supplying aprocess gas into the chamber 30, and a gas exhaust port 34 b forexhausting the process gas out of the chamber 30. The gas feed port 34 ais connected to the process gas supply portion 16, and the gas exhaustport 34 b is connected to an exhaust unit 32. Through the process gassupply portion 16, a mixture gas of ozone and water vapor is supplied orozone is solely supplied while water vapor is stopped. Further, N₂ gascan be further supplied as a dilution gas through the process gas supplyportion 16.

When a wafer W is processed by a process gas, the pressure inside thechamber 30 is preferably maintained at a constant positive pressure. Forthis purpose, the lower container 41 a and lid 41 b is supplied with notonly a pressing force by the cylinder 43, but also a clamping force by alock mechanism 35 through projecting portions 47 a and 47 b respectivelydisposed on end sides of the lower container 41 a and lid 41 b.

The lock mechanism 35 includes a support shaft 52, a rotary tube 55rotatable by a rotator unit 54, a circular plate 56 fixed to the rotarytube 55, and pinching devices 57 disposed at the rim of the circularplate 56. Each of the pinching devices 57 includes press rollers 59 aand 59 b and a roller holding member 48 which holds rotary shafts 58.

The projecting portions 47 a and 47 b are equidistantly disposed at fourpositions, between which gap portions 49 are defined. The projectingportions 47 a and 47 b of each set are disposed at positions overlappingwith each other. When the pinching devices 57 are positioned in the gapportions 49, the lid 41 b can be freely moved up and down.

When the circular plate 56 is rotated along with the rotary tube 55 by apredetermined angle, the press rollers 59 b are stopped at the top facesof the projecting portions 47 b, while the press rollers 59 a arestopped under the projecting portions 47 a. The other denaturing unitshave exactly the same structure.

Next, a detailed explanation will be given of the structure of thesilylation unit (SCH) 11 a with reference to the schematic sectionalview shown in FIG. 7. The silylation unit (SCH) 11 a includes a chamber61 for accommodating a wafer W. The chamber 61 is formed of a stationarylower container 61 a, and a lid 61 b that covers the lower container 61a. The lid 61 b is movable up and down by an elevating unit (not shown).The lower container 61 a includes a hot plate 62, around which nitrogengas with vapor of a silylation agent carried therein, such as DMSDMA(Dimethylsilyldimethylamine), is supplied into the chamber 61. DMSDMA isvaporized into a gaseous state by a vaporizer 63, and carried by N₂ gasinto the chamber 61.

The hot plate 62 is provided with a heater 62 a built therein, by whichthe hot plate 62 is adjustable in temperature within a range of, e.g.,from a room temperature to 200° C. The hot plate 62 is provided withpins 64 on the surface to support a wafer W. Where a wafer W is mountednot directly on the hot plate 62, the wafer W is prevented from beingcontaminated on its bottom. The lower container 61 a is provided withfirst seal rings 65 disposed on the top face of the peripheral portion.The lid 61 b is provided with second seal rings 66 disposed on thebottom face of the peripheral portion. When the lid 61 b is pressedagainst the lower container 61 a, the second seal rings 66 come intocontact with the first seal rings 65. Two pairs of first and second sealrings 65 and 66 are disposed on inner and outer sides, and the spacedefined between the two pairs can be pressure-reduced. When the pressureof this space is reduced, it is ensured that the chamber 61 is airtight.The lid 61 b has an exhaust port 67 essentially at the center forexhausting nitrogen gas with DMSDMA carried therein supplied into thechamber 61. The exhaust port 67 is connected to a vacuum pump 69 througha pressure adjusting unit 68.

In this embodiment, as described later, the control section 26 ispreferably arranged to control the heater 62 a to heat a wafer W beforeand/or after a silylation agent starts being supplied into the chamber.The heating temperature at this time is preferably set to be 50 to 150°C.

In FIG. 7, liquid DMSDMA is vaporized by the vaporizer 63, and carriedby N₂ gas into the chamber 61. Alternatively, vaporized DMSDMA gas(i.e., DMSDMA vapor) may be solely supplied into the chamber 61. WhenDMSDMA is supplied into the chamber 61, the interior of the chamber 61is maintained at a predetermined vacuum level. Accordingly, utilizingthe pressure difference between the vaporizer 63 and chamber 61, DMSDMAgas is easily supplied into the chamber 61. The silylation unit (SCH) 11b has exactly the same structure as the silylation unit (SCH) 11 a.

Next, a detailed explanation will be given of the structure of thecleaning unit 12 a with reference to the schematic sectional view shownin FIG. 8. The cleaning unit (CNU) 12 a includes an annular cup (CP)disposed at the center, and a spin chuck 71 disposed inside the cup(CP). The spin chuck 71 is arranged to fix and hold a wafer W by meansof vacuum suction, and to be rotated by a drive motor 72 in this state.A drain line 73 is disposed at the bottom of the cup (CP) to exhaust thecleaning liquid and purified water.

The drive motor 72 is disposed to be movable up and down in an opening74 a formed in the unit bottom plate 74. The drive motor 72 is coupledwith an elevating mechanism 76, such as an air cylinder, and a verticalguide 77 through a cap-like flange member 75.

The drive motor 72 is provided with a cylindrical cooling jacket 78attached on its side. The flange member 75 is attached to cover theupper half of the cooling jacket 78.

When a chemical liquid or the like is supplied onto a wafer W, the lowerend 75 a of the flange member 75 comes into close contact with the unitbottom plate 74 near the rim of the opening 74 a to make the unitinterior airtight. When a wafer W is transferred between the spin chuck71 and wafer transfer arm 14 a, the drive motor 72 and spin chuck 71 aremoved up by the elevating mechanism 76, so that the lower end 75 a ofthe flange member 75 is separated upward from the unit bottom plate 74.

A cleaning liquid supply mechanism 80 is disposed above the cup (CP) tosupply a predetermined cleaning liquid onto the surface of a wafer W.The cleaning liquid is used for dissolving a substance denatured by oneof the denaturing units (VOS) 15 a to 15 f, such as a denatured resistfilm, present on the wafer.

The cleaning liquid supply mechanism 80 includes a cleaning liquiddelivery nozzle 81, the cleaning liquid supply portion 17 describedabove, a scan arm 82, a vertical support member 85, and an X-axisdriving mechanism 96. The cleaning liquid delivery nozzle 81 is arrangedto deliver the cleaning liquid onto the surface of a wafer W held on thespin chuck 71. The cleaning liquid supply portion 17 is arranged tosupply the predetermined cleaning liquid to the cleaning liquid deliverynozzle 81. The scan arm 82 is arranged to hold the cleaning liquiddelivery nozzle 81, and to be movable back and forth in the Y-direction.The vertical support member 85 is arranged to support the scan arm 82.The X-axis driving mechanism 96 is disposed on a guide rail 84 extendingin the X-axis direction on the unit bottom plate 74, and is arranged toshift the vertical support member 85 a in the X-axis direction. The scanarm 82 is movable in the vertical direction (Z-direction) by a Z-axisdriving mechanism 97, so that the cleaning liquid delivery nozzle 81 canbe moved to an arbitrary position above a wafer W, and retreated to apredetermined position outside the cup (CP).

The cleaning liquid supply portion 17 can selectively supply one of adissolving/removing liquid and a rinsing liquid consisting of purifiedwater to the cleaning liquid delivery nozzle 81. The dissolving/removingliquid is used for dissolving a denatured substance, such as asacrificial film, denatured by one of the denaturing units (VOS) 15 a to15 f, and comprises, e.g., dilute hydrofluoric acid or an amine-basedchemical solution. The cleaning units (CNU) 12 b to 12 d have exactlythe same structure as the cleaning unit (CNU) 12 a.

Next, an explanation will be given of a semiconductor devicemanufacturing process employing a single damascene method, performed bythe semiconductor device manufacturing system shown in FIG. 2. FIG. 9 isa flowchart showing a manufacturing process of this kind. FIGS. 10A to10H are sectional views showing steps of the flow shown in FIG. 9.

At first, a wafer W is prepared from an Si substrate (not shown) asfollows. Specifically, an insulating film 120 is disposed on thesubstrate. A lower interconnection line 122 made of copper is disposedat an upper portion in the insulating film 120 with a barrier metallayer 121 interposed therebetween. A stopper film (such as an SiN filmor SiC film) 123 is disposed on the insulating film 120 and lowerinterconnection line 122 made of copper. Then, the wafer W istransferred into the SOD apparatus 101, in which an inter-levelinsulating film (which will be referred to as a Low-k film, hereinafter)124 made of a low dielectric constant material (Low-k material) isformed on the stopper film 123 (Step 1). Consequently, the state shownin FIG. 10A is obtained.

Then, the wafer W with the Low-k film 124 formed thereon is transferredinto the resist coating/development apparatus 102, in which ananti-reflective coating 125 a and a resist film 125 b are sequentiallyformed on the Low-k film 124. Then, the wafer W is transferred into thelight exposure apparatus 103, in which the wafer W is subjected to alight exposure process with a predetermined pattern. Then, the wafer Wis transferred back into the resist coating/development apparatus 102,in which the resist film 125 b is subjected to a development process bythe developing unit to form a predetermined circuit pattern on theresist film 125 b (Step 2). Consequently, the state shown in FIG. 10B isobtained.

Then, the wafer W is transferred into the etching apparatus 105, inwhich an etching process is performed on the wafer W (Step 3).Consequently, a via-hole 128 a reaching the stopper film 123 is formedin the Low-k film 124 (FIG. 10C).

The wafer W thus treated by the etching process is transferred into thedenaturing/cleaning/recovering apparatus 104, in which the wafer W isfirst processed by one of the denaturing units (VOS) 15 a to 15 f. Inthis process, a gas containing ozone, such as a mixture gas of ozone andwater vapor or ozone alone, is used to denature the anti-reflectivecoating 125 a and resist film 125 b into denatured films 125 a′ and 125b+, which are soluble in water or a predetermined chemical liquid (Step4 and FIG. 10D).

Specifically, at first, a wafer W present at a predetermined positionwithin a carrier C is transferred into the wafer mount unit (TRS) 13 b.Then, the wafer W placed in the wafer mount unit (TRS) 13 b istransferred by the wafer transfer arm 14 a into one of the denaturingunits (VOS) 15 a to 15 f (e.g., 15 a). At this time, while the lid 41 bis retreated above the lower container 41 a, the wafer W is inserted ata position slightly higher than the portions for supporting the wafer Win the hook members 46 attached to the lid 41 b (portions extending inthe horizontal direction), and is transferred onto the hook members 46.Then, the lid 41 b is moved down to bring the lid 41 b into closecontact with the lower container 41 a, and the lock mechanism 35 isfurther operated to set the chamber 30 in an airtight state. When thelid 41 b is moved down, the wafer W is transferred from the hook members46 onto the proximity pins 44 on the way. Then, the stage 33 ismaintained at a predetermined temperature by the heaters 45 a and 45 b.At this time, the temperature of the wafer or substrate is preferablyset to be 100 to 150°, and typically at 105° C.

When the stage 33 and lid 41 b are set at predetermined temperatures,and the temperature distribution of the wafer W becomes essentiallyuniform, an ozone/nitrogen mixture gas (with an ozone content of 9% andat a flow rate of 4 L/min, for example) is first solely supplied fromthe process gas supply portion 16 into the chamber 30. At this time, thegas is adjusted such that the chamber 30 is filled with theozone/nitrogen mixture gas to have a predetermined pressure.Specifically, the ozone concentration is preferably set to be 1 to 20%,and typically at 9%. Where the concentration is set at 9%, the ozoneflow rate is preferably set to be 1 to 10 L/min, and typically at 4L/min. The pressure inside the chamber 30 is preferably set to be 200kPa or less, so as to be a predetermined positive pressure. Thereafter,a process gas prepared by mixing water vapor with the ozone/nitrogenmixture gas is supplied from the process gas supply portion 16 into thechamber 30. At this time, the water vapor flow rate is preferably set tobe 0 to 10 mL/min, and typically at 5 mL/min. Where the water vapor flowrate is set at 0 mL/min, the process is performed only by theozone/nitrogen mixture gas. With this process gas, the anti-reflectivecoating 125 a and resist film 125 b formed on the wafer W are denaturedto be easily dissolved in water or a specific chemical liquid. At thistime, the process time is set to be, e.g., 30 to 600 sec, and typicallyat 300 sec.

When the process using the process gas on the wafer W is finished, thesupply of the process gas is stopped. Further, nitrogen gas is suppliedfrom the process gas supply portion 16 into the chamber 30 to purge theinterior of the chamber 30 with nitrogen gas. This purge process isperformed to completely exhaust the ozone/nitrogen mixture gas even fromthe exhaust unit 32, so that no ozone/nitrogen mixture gas flows fromthe exhaust unit 32 back into the chamber 30 and leaks out of thechamber 30 when the chamber 30 is opened thereafter.

The wafer W treated by the denaturing process is transferred into one ofthe cleaning units (CNU) 12 a to 12 d, in which a dissolving/removingprocess is performed to remove the denatured films 125 a′ and 125 b′,i.e., the denatured anti-reflective coating and the denatured resistfilm (Step 5 and FIG. 10E). At this time, where the anti-reflectivecoating 125 a and resist film 125 b have been denatured to be soluble inwater, they can be dissolved and removed by supplying purified water.Alternatively, where they have been denatured to be soluble in apredetermined chemical liquid instead of water, they can be dissolvedand removed by supplying this chemical liquid.

When the anti-reflective coating 125 a and resist film 125 b areremoved, as described above, the sidewall of the via-hole 128 a formedin the Low-k film 124 is damaged, so damaged portions 129 a are formed,as shown in FIG. 10E. Specifically, as shown in FIG. 11, the Low-k film124 that has methyl groups (Me) as end groups and thus is hydrophobicreacts with moisture during the denaturing process. Consequently, thenumber of methyl groups is decreased and the number of hydroxyl groupsis increased near the sidewall of the via-hole 128 a, so the film isdamaged and increases the dielectric constant.

Although FIG. 10E schematically shows a damaged portion 129 a, theboundary between the damaged portion 129 a and non-damaged portion isnot clear unlike the drawings.

If the via-hole 128 a with the damaged portions 129 a formed in thesidewall is filled with a metal material to form a connection line,problems arise such that the parasitic capacitance betweeninterconnection lines is increased, so a signal delay occurs and theinsulation between interconnection lines is deteriorated.

Accordingly, after the resist film and so forth are removed, in order torecover the damage of the Low-k film 124, the wafer W is transferredinto one of the silylation units (SCH) 11 a and 11 b, in which asilylation process is performed as a recovery process for the damagedportions (Step 6 and FIG. 10F). This process allows the damage to berecovered, so that the specific dielectric constant of the Low-k film124 is returned to a state near the initial state. The conditions of thesilylation process are suitably selected in accordance with the type ofthe silylation agent (silylation gas), as follows. For example, thetemperature of the vaporizer 63 is set to be from a room temperature to50° C. The silylation agent flow rate is set to be 0.1 to 1.0 g/min. TheN₂ gas (purge gas) flow rate is set to be 1 to 10 L/min. The processpressure is set to be 666 to 96,000 Pa (5 to 720 Torr). The temperatureof the hot plate 62 is set to be from a room temperature to 200° C.

In this case, before the silylation agent is supplied, heating(pre-baking) of the wafer W is preferably performed by the heater 62 a.With this heating, moisture remaining on the wafer W is removed toadjust the moisture amount. If the silylation agent is supplied whilethe amount of moisture remaining on the wafer W is too much, thesilylation agent reacts with H₂O, thereby generating particles anddeteriorating the process. This problem about process deterioration canbe prevented by performing pre-baking of the wafer W. However, if thepre-baking temperature is too high, the Low-k film damaged by the resistremoval and so forth causes the following dehydration condensation,which inhibits a silylation reaction when the silylation gas is suppliedthereafter.

—Si—OH+OH—Si—→—Si—O—Si—+H₂O

This pre-baking is preferably performed under reduced pressure or lowhumidity condition at the predetermined time. The pre-baking under abovecondition leads to higher effect.

Further, if the silylation agent (silylation gas) is supplied while thewafer W is being heated higher than a predetermined temperature, thereaction proceeds only around the surface of the wafer W. On the otherhand, where the silylation agent is supplied while the wafer W is beingheated at a suitably lower temperature, the silylation agent enters finepores of the Low-k film, which is particularly prominent in a porousLow-k film with a low dielectric constant. Consequently, the silylationreaction takes place inside the film, and the damage recovery is therebyfurther promoted.

In light of these factors, where the pre-baking is performed, thetemperature of the wafer W is set to be 50° C. or more to provide theeffect described above, and to be 200° C. or less to prevent theproblems described above. In other words, the temperature is preferablyset to be 50 to 200° C.

After the silylation agent starts being supplied, the wafer W ispreferably heated to promote the reaction. At this time, the wafertemperature is preferably set to be 50 to 150° C. to suitably bring outthe effect of promoting the reaction.

Although some of the effect may be provided by performing only one ofthe heating (preheating) before starting supply of the silylation agentand the heating after starting supply of the silylation agent, theeffect is enhanced by performing both of them. In this case, the heatingtemperature after starting supply of the silylation agent is preferablyset to be higher than the heating temperature before starting supply ofthe silylation agent. In order to realize such a two-step heating, thefollowing method may be used. Specifically, the hot plate 62 is heatedin advance by the heater 62 a to a second temperature corresponding tothe temperature necessary after starting supply of the silylation agent.Then, the wafer W is supported by lifter pins (not shown in FIG. 7) setat a raised position, so that the wafer W is heated to a firsttemperature lower than the second temperature. Then, after startingsupply of the silylation agent, the wafer is moved down, so that thewafer W is heated to the second temperature. Alternatively, thefollowing method may be adopted. Specifically, the pre-baking isperformed while the wafer is placed on a table and is heated to thefirst temperature by a lamp disposed as heating means. Then, afterstarting supply of the silylation agent, the output to the lamp isincreased to heat the wafer to the second temperature.

Where DMSDMA is used as the silylation agent, the following method maybe used, for example. Specifically, the hot plate 62 is set at apredetermined temperature, and the inner pressure of the chamber 61 isdecreased to 5 Torr (=666 Pa). Then, DMSDMA vapor carried by nitrogengas is supplied into the chamber 61 until the inner pressure reaches 55Torr. Then, the process is performed for, e.g., three minutes, whilemaintaining the pressure. The silylation reaction using DMSDMA isexpressed by the following reaction formula.

The silylation agent is not limited to DMSDMA described above, and theagent may comprise any substance as long as it causes a silylationreaction. However, it is preferable to use a substance having arelatively small molecular structure selected from the compoundsincluding silazane bonds (Si—N bonds) in molecules, such as a substancehaving a molecular weight preferably of 260 or less, and more preferablyof 170 or less. Namely, examples other than DMSDMA and HMDS are TMSDMA(Dimethylaminotrimethylsilane), TMDS (1,1,3,3-Tetramethyldisilazane),TMSPyrole (1-Trimethylsilylpyrole), BSTFA(N,O-Bis(trimethylsilyl)trifluoroacetamide), and BDMADMS(Bis(dimethylamino)dimethylsilane). The chemical structures of thesesubstances are as follows.

Of the compound set out above, TMSDMA and TMDS are preferably used,because they are high in the effect of recovering the dielectricconstant, and the effect of decreasing the leakage current. Further, inlight of the stability after silylation, it is preferable to use asubstance (such as TMSDMA or HMDS) having a structure in which Si ofeach silazane bond is bonded to three alkyl groups (such as methylgroups).

In order to enhance the recovering effect of the silylation process, acleaning process by a chemical liquid, such as an alkaline chemicalsolution, is preferably performed after the resist film is removed, andbefore the silylation process is performed.

The wafer W thus treated by the silylation process is transferred intothe etching apparatus 105, in which an etching process is performed toremove the stopper film 123 (Step 7 and FIG. 10G). Then, the wafer W istransferred into the denaturing/cleaning/recovering apparatus 104, inwhich a cleaning process is performed by one of the cleaning units (CNU)12 a to 12 d (Step 8). The Low-k film 124 may be damaged by the etchingprocess and/or cleaning process. In this case, a silylation process maybe performed in the same manner as described above.

Thereafter, the wafer W is transferred into the sputtering apparatus106, in which a barrier metal film and a Cu seed layer (i.e., platingseed layer) are formed on the inner surface of the via-hole 128 a. Then,the wafer W is transferred into the electrolytic plating apparatus 107,in which copper 126 used as an interconnection line metal is embedded inthe via-hole 128 a by electrolytic plating (Step 9 and FIG. 10H). Then,the wafer W is subjected to a heat process to perform an annealingprocess of the copper 126 embedded in the via-hole 128 a (no annealingapparatus is shown in FIG. 2). Then, the wafer W is transferred into theCMP apparatus 109, in which a planarization process is performed on thewafer W by a CMP method (Step 10). Consequently, a predeterminedsemiconductor device is manufactured.

As described above, where a semiconductor device is manufactured, thedenaturing process and cleaning process are performed by a process gascontaining ozone. Consequently, as compared to a case where ashing isused, the Low-k film is less damaged when the resist film and so forthare removed. Further, since the silylation process provides an excellenteffect of recovering the damage, the specific dielectric constant of thefilm is sufficiently recovered. Consequently, it is possible to providea semiconductor device with excellent electrical characteristics, and tothereby improve the reliability of the semiconductor device.

Next, an explanation will be given of a semiconductor devicemanufacturing process employing a dual damascene method, performed bythe semiconductor device manufacturing system shown in FIG. 2. FIG. 12is a flowchart showing a manufacturing process of this kind. FIGS. 13Ato 13K are sectional views showing steps of the flow shown in FIG. 12.In this embodiment, the apparatuses used in the respective steps willnot be explained, because they have been clarified by the precedingexplanation.

At first, as in the case using a single damascene method describedabove, a wafer W is prepared from an Si substrate (not shown) asfollows. Specifically, an insulating film 120 is disposed on thesubstrate. A lower interconnection line 122 made of copper is disposedat an upper portion in the insulating film 120 with a barrier metallayer 121 interposed therebetween. A stopper film (such as an SiN filmor SiC film) 123 is disposed on the insulating film 120 and lowerinterconnection line 122 made of copper. Then, a Low-k film 124 made ofa low dielectric constant material (Low-k material) is formed on thestopper film 123 on this wafer W (Step 101 and FIG. 13A).

Then, an anti-reflective coating 125 a and a resist film 125 b aresequentially formed on the Low-k film 124. Then, the wafer W issubjected to a light exposure process with a predetermined pattern.Then, the resist film 125 b is subjected to a development process toform a predetermined circuit pattern on the resist film 125 b (Step 102and FIG. 13B).

Then, an etching process using the resist film 125 b as an etching maskis performed to form a via-hole 128 a reaching the stopper film 123(Step 103 and FIG. 13C).

Then, using a gas containing ozone, such as a mixture gas of ozone andwater vapor or ozone alone, the anti-reflective coating 125 a and resistfilm 125 b are denatured to be soluble in water or a predeterminedchemical liquid (Step 104). Then, using purified water or thepredetermined chemical liquid, the denatured anti-reflective coating andresist film are dissolved and removed (Step 105), thereby obtaining thestate shown in FIG. 13D.

As in the first embodiment, when the anti-reflective coating 125 a andresist film 125 b are removed, as described above, the sidewall of thevia-hole 128 a formed in the Low-k film 124 is damaged, so damagedportions 129 a are formed, as shown in FIG. 13D. Accordingly, as in thefirst embodiment, after the resist film and so forth are removed, inorder to recover the damage of the Low-k film 124, a silylation processis performed as a recovery process on the wafer W for the damagedportions (Step 106 and FIG. 13E).

Then, a protection film (sacrificial film) 131 is formed on the surfaceof the Low-k film 124 (Step 107). Then, an anti-reflective coating 132 aand a resist film 132 b are sequentially formed on the protection film131. Then, the resist film 132 b is subjected to a light exposureprocess with a predetermined pattern, and then to a development processto form a circuit pattern on the resist film 132 b (Step 108 and FIG.13F). The protection film 131 can be formed from a predeterminedchemical liquid applied by spin coating in the SOD apparatus 101. Theprotection film 131 is not necessarily required, so the anti-reflectivecoating 132 a and resist film 132 b may be formed directly on the Low-kfilm 124.

Then, an etching process using the resist film 132 b as an etching maskis performed to form a trench 128 b in the Low-k film 124 (Step 109 andFIG. 13G).

Thereafter, using a gas containing ozone, such as a mixture gas of ozoneand water vapor or ozone alone, the anti-reflective coating 132 a,resist film 132 b, and protection film 131 are denatured to be solublein water or a predetermined chemical liquid (Step 110). Then, usingpurified water or the predetermined chemical liquid, the denaturedanti-reflective coating, resist film, and protection film are dissolvedand removed (Step 111), thereby obtaining the state shown in FIG. 13H.

When the anti-reflective coating 132 a, resist film 132 b, andprotection film 131 are removed, as described above, the sidewall of thetrench 128 b and the sidewall of the via-hole 128 a formed in the Low-kfilm 124 is damaged, so damaged portions 129 b are formed, as shown inFIG. 13H. Accordingly, after the resist film and so forth are removed,in order to recover the damage of the Low-k film 124, a silylationprocess is performed as a recovery process on the wafer W for thedamaged portions (Step 112 and FIG. 13I), as in Step 106.

Then, the wafer W thus treated by the silylation process is subjected toan etching process (Step 113 and FIG. 13J), and then to a cleaningprocess (Step 114), to remove the stopper film 123. The Low-k film 124may be damaged by the etching process and/or cleaning process. In thiscase, a silylation process may be performed in the same manner asdescribed above.

Thereafter, a barrier metal film and a Cu seed layer (i.e., plating seedlayer) are formed on the inner surface of the trench 128 b and via-hole128 a. Then, copper 126 used as an interconnection line metal isembedded in the trench 128 b and via-hole 128 a by electrolytic plating(Step 115 and FIG. 13K). Then, the wafer W is subjected to a heatprocess to perform an annealing process of the copper 126 embedded inthe trench 128 b and via-hole 128 a (no annealing apparatus is shown inFIG. 2). Then, the wafer W is transferred into the CMP apparatus 109, inwhich a planarization process is performed on the wafer W by a CMPmethod (Step 116). Consequently, a predetermined semiconductor device ismanufactured.

As described above, also in a case where a dual damascene method is usedto manufacture a semiconductor device, the denaturing process andcleaning process are performed by a process gas containing ozone, as inthe case where a single damascene method is used. Consequently, ascompared to a case where ashing is used, the Low-k film is less damagedwhen the resist film and so forth are removed. Further, since thesilylation process provides an excellent effect of recovering thedamage, the specific dielectric constant of the film is sufficientlyrecovered. Consequently, it is possible to provide a semiconductordevice with excellent electrical characteristics, and to thereby improvethe reliability of the semiconductor device.

Next, an explanation will be given of results of experiments conductedto confirm effects of the first embodiment.

At first, samples were formed, as shown in FIG. 14A, such that each ofwhich comprised an Si substrate 140 having a low resistivity and a Low-kfilm 141 disposed on the substrate 140. An unprocessed one of thesamples was set as a reference (Sample 1). Another one of the sampleswas processed by ozone and water vapor (Sample 2). Other two of thesamples were processed by ozone and water vapor and then subjected to asilylation process (Samples 3 and 4). Another one of the samples wasprocessed by ozone and water vapor, then processed by an alkalinechemical solution (choline), and then subjected to a silylation process(Sample 5). As shown in FIG. 14B, each of the samples thus prepared wasprovided with an Al-sputtering electrode 142 formed on the Low-k film141. Then, as shown in FIG. 14C, while a voltage was applied between theAl-sputtering electrode 142 and Si substrate 140, the specificdielectric constant and leakage current value of the Low-k film 141 weremeasured.

As the Low-k film, an SOD film or CVD film was used. The process usingozone and water vapor was performed under conditions set at 105° C. and75 kPa. The silylation process was performed under conditions set at150° C. (Condition 1) for Sample 3, under conditions set at 180° C.(Condition 2) for Sample 4, and under conditions set to be the same asCondition 1 for Sample 5.

Table 1 shows results of this experiment. As shown in Table 1, thefollowing matters were confirmed. Specifically, where the process usingozone and water vapor was performed, the specific dielectric constantand leakage current value were increased. However, where the silylationprocess was further performed as a recovery process, the specificdielectric constant and leakage current value became almost equal tothose of the reference. In the case of Sample 5 where the alkalinechemical solution cleaning and silylation process were sequentiallyperformed, the specific dielectric constant was further decreased. Itshould be noted that Sample 1 used as the reference rendered a specificdielectric constant slightly higher than the inherent value of thematerial, because Sample 1 had some denatured part left in the surfacelayer.

TABLE 1 Specific dielectric Leakage Sample constant current value No.Conditions (k-value) (A/cm²) 1 Reference 2.55 1.9 × 10⁻¹⁰ 2 Ozone andwater 4.51 9.5 × 10⁻⁵  vapor process 3 Ozone and water 2.69 4.3 × 10⁻¹⁰vapor process + Silylation process (Condition 1) 4 Ozone and water 2.673.7 × 10⁻¹⁰ vapor process + Silylation process (Condition 2) 5 Ozone andwater 2.35 7.8 × 10⁻¹⁰ vapor process + Cleaning process + Silylationprocess

Next, an experiment was conducted to confirm the influence of thepresence or absence of the water vapor in the ozone process.

At first, samples were formed to have the structure shown in FIG. 14A.An unprocessed one of the samples was set as a reference (Sample 6).Another one of the samples was processed by ozone and water vapor underCondition 1 described above (Sample 7). Another one of the samples wasfurther processed by a silylation process in addition to the processgiven to Sample 7 (Sample 8). Another one of the samples was processedunder the same conditions used for Sample 7 but excluding water vapor(Sample 9). Another one of the samples was further processed by asilylation process in addition to the process given to Sample 9 (Sample10). Another one of the samples was processed by etching and O₂-ashingin this order to form a comparative example (Sample 11). Another one ofthe samples was further processed by a silylation process in addition tothe process given to Sample 11 to form another comparative example(Sample 12). Then, as described above, each of the samples thus preparedwas provided with an Al-sputtering electrode, and the specificdielectric constant and leakage current value of the Low-k film weremeasured. The material of the Low-k film and the conditions of thesilylation process were set to be the same as those described above.

Table 2 shows results of this experiment. As shown in Table 2, thefollowing matters were confirmed. Specifically, where the process wasperformed solely using ozone without using water vapor, the specificdielectric constant and leakage current value were increased, as in acase where the process was performed using ozone and water vapor.However, the increased degree was smaller and thus damage was smaller inthe case solely using ozone without using water vapor. Where thesilylation process was further performed as a recovery process, thespecific dielectric constant and leakage current value became almostequal to those of the reference. Further, where the etching andO₂-ashing were performed, the recovery degree obtained by the silylationprocess was lower, as compared to a case where the ozone process wasperformed.

TABLE 2 With or Specific Leakage Removing without dielectric currentSample process silylation constant value No. conditions process(k-value) (A/cm²) 6 Reference 2.45 4.83 × 10⁻⁹ 7 Ozone + Water Without3.55 5.03 × 10⁻⁷ vapor 8 Ozone + Water With 2.79 2.05 × 10⁻⁹ vapor 9Ozone alone Without 3.19 8.22 × 10⁻⁸ 10 Ozone alone With 2.73 4.43 ×10⁻⁹ 11 Etching + O₂— Without 3.40 3.10 × 10⁻⁵ ashing 12 Etching + O₂—With 2.95 7.60 × 10⁻⁸ ashing

Next, an explanation will be given of a second embodiment.

FIG. 15 is an explanatory view schematically showing the arrangement ofa semiconductor device manufacturing system used for a semiconductordevice manufacturing process according to a second embodiment of thepresent invention. In FIG. 15, the same constituent elements as thosedescribed above are denoted by the same reference numerals used in FIG.2. This semiconductor device manufacturing system includes a processsection 100′ and a main control section 110 having the same structure asthat shown in FIG. 2. The process section 100′ includes an SOD (Spin OnDielectric) apparatus 101, a resist coating/development apparatus 102, alight exposure apparatus 103, a sputtering apparatus 106, anelectrolytic plating apparatus 107, and a CMP apparatus 109 used as apolishing apparatus, which are the same as those in the firstembodiment. The process section 100′ further includes anetching/ashing/recovering apparatus 108 for performing dry etching, dryashing, and recovery processes, and a cleaning apparatus 104′.

In other words, the semiconductor device manufacturing system accordingto this embodiment differs from the semiconductor device manufacturingsystem according to the first embodiment, in that theetching/ashing/recovering apparatus 108 and cleaning apparatus 104′ aredisposed in place of the etching apparatus 105 anddenaturing/cleaning/recovering apparatus 104 shown in FIG. 2.

The cleaning apparatus 104′ includes a cleaning unit shown in FIG. 8, aheating mechanism, and a transfer system, to perform a cleaning processon a wafer W.

The etching/ashing/recovering apparatus 108 is arranged to perform, asdescribed later, dry etching for forming a via-hole or trench with apredetermined pattern in an inter-level insulating film (Low-k film),dry ashing for removing a resist film, and a recovery process forrecovering damage of an inter-level insulating film. These processes canbe sequentially performed as dry processes in a vacuum.

FIG. 16 is a plan view schematically showing the structure of theetching/ashing/recovering apparatus 108. The etching/ashing/recoveringapparatus 108 includes etching units 151 and 152 for performing dryetching (plasma etching), an ashing unit 153 for performing dry ashing(plasma ashing), and a silylation unit (SCH) 154. These units 151 to 154are disposed to respectively correspond to four sides of a hexagonalwafer transfer chamber 155. The other two sides of the wafer transferchamber 155 are respectively connected to load-lock chambers 156 and157. A wafer I/O (in/out) chamber 158 is connected to the load-lockchambers 156 and 157 on the side opposite to the wafer transfer chamber155. The wafer I/O chamber 158 has three ports 159, 160, and 161 on theside opposite to the load-lock chambers 156 and 157, wherein the portsare used for respectively connecting three carriers C that can containwafers W.

The etching units 151 and 152, ashing unit 153, silylation unit (SCH)154, and load-lock chambers 156 and 157 are connected to the sides ofthe wafer transfer chamber 155 respectively through gate valves G, asshown in FIG. 16. Each of these units and chambers communicates with thewafer transfer chamber 155 when the corresponding gate valve G isopened, and is blocked from the wafer transfer chamber 155 when thecorresponding gate valve G is closed. Gate valves G are also disposedbetween the load-lock chambers 156 and 157 and the wafer I/O chamber158. Each of the load-lock chambers 156 and 157 communicates with thewafer I/O chamber 158 when the corresponding gate valve G is opened, andis blocked from the wafer I/O chamber 158 when the corresponding gatevalve G is closed.

The wafer transfer chamber 155 is provided with a wafer transfer unit162 disposed therein, for transferring wafers W to and from the etchingunits 151 and 152, ashing unit 153, silylation unit (SCH) 154, andload-lock chambers 156 and 157. The wafer transfer unit 162 is disposedessentially at the center of the wafer transfer chamber 155. The wafertransfer unit 162 includes two rotation/stretch portions 163, which arerotatable and extensible/contractible. Two blades 164 a and 164 b, eachfor supporting a wafer W, are respectively connected to the distal endsof the rotation/stretch portions 163. The two blades 164 a and 164 b areconnected to the rotation/stretch portions 163 to face oppositedirections. The interior of the wafer transfer chamber 155 can bemaintained at a predetermined vacuum level.

The wafer I/O chamber 158 is provided with a HEPA filter (not shown)disposed on the ceiling, and clean air is supplied through the HEPAfilter into the wafer I/O chamber 158 in a down flow state. A wafer W istransferred to and from the wafer I/O chamber 158 within a clean airatmosphere under atmospheric pressure. Each of the three ports 159, 160,and 161 of the wafer I/O chamber 158 for connecting a carrier C isprovided with a shutter (not shown). A carrier C, which contains wafersW or is empty, is directly connected to each of the ports 159, 160, and161, and the shutter is then opened for the carrier C to communicatewith the wafer I/O chamber 158 while preventing inflow of outside air.An alignment chamber 165 for performing alignment of a wafer W isdisposed on one side of the wafer I/O chamber 158.

The wafer I/O chamber 158 is provided with a wafer transfer unit 166disposed therein, for transferring wafers W to and from the carriers Cand load-lock chambers 156 and 157. The wafer transfer unit 166 includesarticulated arm structures respectively having hands 167 at the distalends. The wafer transfer unit 166 is movable on a rail 168 in adirection in which the carriers C are arrayed, to transfer a wafer Wplaced on each of the hands 167 at the distal ends. A control section169 is arranged to control the operation of the wafer transfer units 162and 166 and the entire system.

Next, an explanation will be given of the respective units.

At first, the ashing unit 153 will be explained. Since the outline ofthe structure of the etching units 151 and 152 is the same as the ashingunit except for the process gas, the explanation thereof will beomitted.

As schematically shown in the structural view of FIG. 17, this ashingunit 153 is arranged to perform plasma ashing. The ashing unit 153includes an essentially cylindrical process chamber 211. The processchamber 211 is provided with a susceptor 215 disposed therein on thebottom through an insulating plate 213 and a susceptor pedestal 214 inthis order. The susceptor 215 is used as a lower electrode and has a topface provided with an electrostatic chuck 220, on which a wafer W isplaced. A reference numeral 216 denotes a high-pass filter (HPF).

The susceptor pedestal 214 is provided with a temperature adjustingmedium space 217 formed therein for circulating a temperature adjustingmedium to adjust the susceptor 215 to a predetermined temperature. Thetemperature adjusting medium space 217 is connected to a supply line 218and an exhaust line 219. The electrostatic chuck 220 has a structure inwhich an electrode 222 is sandwiched between insulating layers 221. Whena DC (direct current) voltage is applied from a DC power supply 223 tothe electrode, the W is attracted and held on the electrostatic chuck222 by an electrostatic force. Further, a heat transmission gas, such asHe gas, is supplied through a gas passage 224 to the bottom of the waferW. The temperature of the wafer W is adjusted to a predetermined valuethrough the heat transmission gas. An annular focus ring 225 is disposedon the top of the susceptor 215 at the rim to surround the wafer Wplaced on the electrostatic chuck 220.

An upper electrode 231 is disposed above the susceptor 215 to face thesusceptor 215, and is supported inside the plasma process chamber 211through an insulating body 232. The upper electrode 231 includes anelectrode plate 234 having a number of gas delivery holes 233, and anelectrode support 235 supporting the electrode plate 234, such that theyform a shower structure.

The electrode support 235 has a gas feed port 236 formed therein at thecenter, which is connected to a gas supply line 237. The gas supply line237 is connected to a process gas supply source 240 for supplying anashing process gas through a valve 238 and a mass-flow controller 239.The ashing process gas, such as O₂ gas, NH3 gas, or CO₂ gas, is suppliedfrom the process gas supply source 240 into the process chamber 211.

The bottom of the process chamber 211 is connected to an exhaust unit245 through an exhaust line 241. The exhaust unit 245 includes a vacuumpump, such as a turbo molecular pump, to set the interior of the processchamber 211 at a predetermined vacuum atmosphere. The process chamber211 has a gate valve 242 on the sidewall.

The upper electrode 231 is connected to a first RF (radio frequency)power supply 250 through a first matching unit 251 to supply an RF powerfor plasma generation. The upper electrode 231 is further connected to alow-pass filter (LPF) 252. On the other hand, the lower electrode orsusceptor 215 is connected to a second RF power supply 260 through asecond matching unit 261 to attract ions in plasma for the ashing toproceed.

In the ashing unit 153 thus structured, a predetermined ashing processgas is supplied from the process gas supply source 240 into the chamber211, and is turned into plasma by an RF power applied from the first RFpower supply 250. This plasma is used to ash a resist film and so forthpresent on the wafer W.

Next, a detailed explanation will be given of the silylation unit (SCH)154 with reference to the schematic sectional view shown in FIG. 18. Thesilylation unit (SCH) 154 includes a chamber 301 for accommodating awafer W. The chamber 301 is provided with a wafer table 302 disposedtherein at the bottom. The wafer table 302 includes a heater 303 builttherein, by which the wafer W placed on the wafer table 302 can beheated at a predetermined temperature. The wafer table 302 is providedwith wafer lifter pins 304, which can project and retreat to and fromthe top face. The lifter pins 304 can place the wafer W at apredetermined position above and separated from the wafer table 302,when the wafer W is transferred to and from the wafer table 302.

The chamber 301 contains an internal container 305, which defines anarrow process space S for accommodating the wafer W. A silylation agent(silylation gas) is supplied into this process space S. The internalcontainer 305 has a gas feed passage 306 formed at the center andextending in a vertical direction.

The top of the gas feed passage 306 is connected to a gas supply line307. The gas supply line 307 is connected to a line 309 extending from asilylation agent supply source 308 for supplying a silylation agent,such as DMSDMA (Dimethylsilyldimethylamine), and a line 311 extendingfrom a carrier gas supply source 310 for supplying a carrier gas, suchas Ar or N₂ gas. The line 309 is provided with a vaporizer 312 forvaporizing the silylation agent, a mass-flow controller 313 and aswitching valve 314 disposed thereon in this order from the silylationagent supply source 308. The line 311 is provided with a mass-flowcontroller 315 and a switching valve 316 disposed thereon in this orderfrom the carrier gas supply source 310. The silylation agent vaporizedby the vaporizer 312 is carried by the carrier gas and is suppliedthrough the gas supply line 307 and gas feed passage 306 into theprocess space S defined by the internal container 305. When the processis performed, the wafer W is heated by the heater 303 to a predeterminedtemperature. In this case, the wafer temperature can be controlledwithin a range of, e.g., from a room temperature to 300° C.

An atmospheric gas supply line 317 is disposed to extend from theatmospheric environment outside the chamber 301 to the internalcontainer 305 inside the chamber 301. The atmospheric gas supply line317 is provided with a valve 318 disposed thereon. When the valve 318 isopened, atmospheric gas comes into the process space S defined by theinternal container 305 inside the chamber 301. Consequently,predetermined moisture is supplied onto the wafer W.

The chamber 301 has a gate valve 319 disposed on the sidewall. When thegate valve 319 is opened, the wafer W is transferred to and from thechamber 301. The bottom of the chamber 301 is connected to a vacuum pump(not shown) through an exhaust line 320 disposed at the periphery. Theinterior of the chamber 301 is exhausted by the vacuum pump through theexhaust line 320 and thereby controlled to have a pressure of, e.g., 10Torr (266 Pa) or less. A cold trap 321 is disposed on the exhaust line320. A baffle plate 322 is disposed between an upper portion of thewafer table 302 and the chamber wall.

The etching/ashing/recovering apparatus 108 is arranged to sequentiallyperform the etching, ashing, recovery process in a vacuum atmosphere.Accordingly, moisture is scarcely present in the space accommodating thewafer W as it is. In this state, the silylation unit (SCH) 153 maysuffer a difficulty in causing the silylation reaction described aboveto attain a sufficient recovery effect. In light of this, as explainedlater in detail, the control section 169 performed the followingcontrol. Specifically, before starting supply of the silylation agent,the valve 318 on the atmospheric gas supply line 317 is opened to supplyatmospheric gas so that moisture is adsorbed on the wafer W. Thereafter,the wafer W on the wafer table 302 is heated by the heater 303 toperformed moisture adjustment, and then the silylation agent issupplied. At this time, the heating temperature is preferably set to be50 to 200° C. In order to promote the silylation reaction, the wafer Wmay be heated also after starting supply of the silylation agent.

Next, an explanation will be given of a semiconductor devicemanufacturing process employing a single damascene method, performed bythe semiconductor device manufacturing system shown in FIG. 15. FIG. 19is a flowchart showing a manufacturing process of this kind. FIGS. 20Ato 20G are sectional views showing steps of the flow shown in FIG. 19.In this process, since the film structures in manufacturing asemiconductor device are the same as those shown in FIGS. 10A to 10K,the same films described above are denoted by the same referencenumerals used in FIGS. 10A to 10K.

At first, a wafer W is prepared from an Si substrate (not shown) asfollows. Specifically, an insulating film 120 is disposed on thesubstrate. A lower interconnection line 122 made of copper is disposedat an upper portion in the insulating film 120 with a barrier metallayer 121 interposed therebetween. A stopper film (such as an SiN filmor SiC film) 123 is disposed on the insulating film 120 and lowerinterconnection line 122 made of copper. Then, the wafer W istransferred into the SOD apparatus 101, in which an inter-levelinsulating film (which will be referred to as a Low-k film, hereinafter)124 made of a low dielectric constant material (Low-k material) isformed on the stopper film 123 (Step 201). Consequently, the state shownin FIG. 20A is obtained.

Then, the wafer W with the Low-k film 124 formed thereon is transferredinto the resist coating/development apparatus 102, in which ananti-reflective coating 125 a and a resist film 125 b are sequentiallyformed on the Low-k film 124. Then, the wafer W is transferred into thelight exposure apparatus 103, in which the wafer W is subjected to alight exposure process with a predetermined pattern. Then, the wafer Wis transferred back into the resist coating/development apparatus 102,in which the resist film 125 b is subjected to a development process bythe developing unit to form a predetermined circuit pattern on theresist film 125 b (Step 202). Consequently, the state shown in FIG. 20Bis obtained.

Then, the wafer W is transferred into the etching/ashing/recoveringapparatus 108, in which etching, ashing, and a recovery process aresequentially performed as dry processes in a vacuum. Specifically, atfirst, the wafer W is transferred into the etching unit 151, in whichplasma etching is performed (Step 203). Consequently, a via-hole 128 areaching the stopper film 123 is formed in the Low-k film 124 (FIG.20C).

The wafer W thus treated by the etching process is transferred into theashing unit 153, in which the anti-reflective coating 125 a and resistfilm 125 b are removed by a plasma ashing process (Step 204 and FIG.20D).

When the anti-reflective coating 125 a and resist film 125 b are removedby plasma ashing, as described above, the sidewall of the via-hole 128 aformed in the Low-k film 124 is damaged, so damaged portions 129 a areformed, as shown in FIG. 20D, as in the first embodiment.

Accordingly, after the resist film and so forth are removed, in order torecover the damage of the Low-k film 124, the wafer W is transferredinto the silylation unit (SCH) 154, in which a silylation process isperformed. In this case, since the damage of the Low-k film 124 causedby the plasma ashing process is larger than the damage caused by thedenaturing process using an ozone-containing gas described above, therecovery process needs to be performed more effectively. However, theetching/ashing/recovering apparatus 108 is arranged to sequentiallyperform the etching, ashing, recovery process in a vacuum atmosphere.Accordingly, moisture is scarcely present in the apparatus as it is,with which the silylation reaction is hardly caused, so the recoveryprocess cannot be effectively performed.

Accordingly, in this embodiment, after the wafer W is transferred intothe silylation unit (SCH) 154 and before the silylation process isperformed, the valve 318 is opened to supply atmospheric gas through theatmospheric gas supply line 317, so as to apply moisture onto the waferW (Step 205).

As described above, atmospheric gas is supplied to apply moisture ontothe wafer W. In this respect, if the moisture amount remaining on thewafer W is too large when a silylation agent is supplied, the silylationagent may react with H₂O and thereby generate particles that deterioratethe process. Accordingly, after atmospheric gas is supplied and beforethe silylation agent is supplied, a heating process (pre-baking) isperformed to adjust the moisture amount (Step 206). At this time, if thepre-baking temperature is too high, the Low-k film damaged by the resistremoval and so forth causes the dehydration condensation describedabove, which inhibits a silylation reaction when the silylation gas issupplied thereafter. Further, as described above, if the silylationagent (silylation gas) is supplied while the temperature of the wafer Wis too high, the reaction proceeds only around the surface of the waferW. On the other hand, where the wafer W is heated at a suitabletemperature, the silylation agent enters fine pores of the Low-k film,which is particularly prominent in a porous Low-k film. Consequently,the silylation reaction takes place inside the film, and the damagerecovery is thereby further promoted. In light of these factors, thepre-baking is preferably performed at a temperature of 50 to 200° C.

This pre-baking is preferably performed under reduced pressure or lowhumidity condition at the predetermined time. The pre-baking under abovecondition leads to higher effect.

After the processes described above, the silylation agent is supplied toperform the silylation process (Step 207 and FIG. 20E). Where thesilylation process is performed after the moisture on the wafer W isadjusted, the damage recovery of the Low-k film 124 is promoted.Accordingly, even where the resist film 125 b and so forth are removedby a process causing a large damage, such as plasma ashing, the specificdielectric constant of the Low-k film 124 is returned to a state nearthe initial state.

Where the silylation process is performed in the silylation unit (SCH)154, at first, the gate valve 319 is opened. Then, the wafer W istransferred into the chamber 301 and placed on the wafer table 302.Then, the pressure inside the chamber 301 is reduced to a predeterminedpressure. In this state, the silylation agent vaporized by the vaporizeris carried by a carrier gas onto the wafer W. The conditions of thesilylation process in the silylation unit (SCH) 154 are suitablyselected in accordance with the type of the silylation agent (silylationgas), as follows. For example, the temperature of the vaporizer 312 isset to be from a room temperature to 200° C. The silylation agent flowrate is set to be 700 scam (mL/min) or less. The process pressure is setto be 10 mTorr to 100 Torr (1.33 to 13,330 Pa). The temperature of thetable 302 is set to be from a room temperature to 200° C.

In order to promote the reaction, the wafer W is preferably heated bythe heater 303 also after starting supply of the silylation agent. Atthis time, the wafer temperature is preferably set to be 50 to 200° C.to suitably bring out the effect of promoting the reaction.

In this case, the heating temperature after starting supply of thesilylation agent is preferably set to be higher than the heatingtemperature before starting supply of the silylation agent. In order torealize such a two-step heating, the following method may be used.Specifically, the wafer table 302 is heated in advance by the heater 303to a second temperature corresponding to the temperature necessary afterstarting supply of the silylation agent. Then, the wafer W is supportedby the lifter pins 304 set at a raised position, and is therebyseparated from the wafer table 302, as shown in FIG. 21A, so that thewafer W is heated to a first temperature lower than the secondtemperature. In this state, as shown in FIG. 21B, the silylation agentstarts being supplied. Then, as shown in FIG. 21C, the lifter pins 304are moved down to place the wafer W on the wafer table 302, so that thewafer W is heated to the second temperature. Alternatively, thefollowing method may be adopted, as described above. Specifically, thepre-baking is performed while the wafer is placed on a table and isheated to the first temperature by a lamp disposed as heating means.Then, after starting supply of the silylation agent, the output to thelamp is increased to heat the wafer to the second temperature.

The wafer W thus treated by the silylation process is transferred intothe etching unit 152, in which an etching process is performed to removethe stopper film 123 (Step 208 and FIG. 20F). Then, the wafer W istransferred into the cleaning apparatus 104′, in which a cleaningprocess is performed (Step 209). The Low-k film 124 may be damaged bythe etching process and/or cleaning process. In this case, a silylationprocess may be performed in the same manner as described above.

Thereafter, as in the first embodiment, the wafer W is transferred intothe sputtering apparatus 106, in which a barrier metal film and a Cuseed layer are formed on the inner surface of the via-hole 128 a. Then,the wafer W is transferred into the electrolytic plating apparatus 107,in which copper 126 used as an interconnection line metal is embedded inthe via-hole 128 a by electrolytic plating (Step 210 and FIG. 20G).Then, the wafer W is subjected to a heat process to perform an annealingprocess of the copper 126 embedded in the via-hole 128 a (no annealingapparatus is shown in FIG. 15). Then, the wafer W is transferred intothe CMP apparatus 109, in which a planarization process is performed onthe wafer W by a CMP method (Step 211). Consequently, a predeterminedsemiconductor device is manufactured.

As described above, where a semiconductor device is manufactured, therecovery process is effectively performed. Accordingly, even where theresist film and so forth are removed by a process causing a largedamage, such as an ashing process, the specific dielectric constant ofthe Low-k film is sufficiently recovered. Consequently, it is possibleto provide a semiconductor device with excellent electricalcharacteristics, and to thereby improve the reliability of thesemiconductor device. Incidentally, the procedures shown in FIG. 19 andFIGS. 20A to 20G can be applied to a case where a semiconductor devicemanufacturing process employs a dual damascene method.

Next, an explanation will be given of results of experiments conductedto confirm effects of the second embodiment.

At first, samples were formed to have the structure shown in FIG. 14A.An unprocessed one of the samples was set as a reference (Sample 21).Another one of the samples was exposed to etching process conditions,and then to ashing conditions representing a resist film removingprocess (Sample 22). Another one of the samples was subjected toatmospheric gas supply and preheating, and then to a silylation processusing a silylation agent supplied thereafter (Sample 23). Another one ofthe samples was further subjected to a heating process after startingsupply of the silylation agent, subsequently to the preheating (Sample24). Then, as shown in FIG. 14B described above, each of the samplesthus prepared was provided with an Al-sputtering electrode 142, and thespecific dielectric constant of the Low-k film 141 was measured while avoltage was applied between the Al-sputtering electrode 142 and Sisubstrate 140.

As the Low-k film, an SOD film was used. The etching process isperformed using CF₄/Ar gas, and the ashing process is performed using O₂gas. The preheating temperature was set at about 100° C., the heatingtemperature after starting supply of the silylation agent was set at150° C.

Table 3 shows results of this experiment. As shown in Table 3, where theLow-k film was exposed to the etching process and ashing process, thespecific dielectric constant of the film was increased from that of thereference. In the case of Sample 23 where the recovery process wasperformed after the atmospheric gas supply and preheating, the specificdielectric constant was recovered by 50%. In the case of Sample 24 wherethe heating was performed after starting supply of the silylation agent,the specific dielectric constant was recovered by 80%.

TABLE 3 Specific Recovery Sample dielectric rate No. Process conditionsconstant (%) 21 After Low-k film 2.40 — formation 22 After ashing 2.66 —23 Preheating + 2.53 50.0 Silylation process 24 Preheating + 2.45 80.8Silylation process + Heating after starting gas supply

In the second embodiment, the resist film is ashed and removed by theashing process using O₂ gas plasma. Alternatively, the resist film maybe removed mainly by oxygen radicals contained in plasma.

In an ordinary ashing process, oxygen ions contained in plasma are drawnby the second RF power supply 260 to promote ashing. In this case, theLow-k film is damaged by oxygen ions, and the surface of the Low-k filmmay be thereby changed to a dense structure. If the Low-k film is dense,a silylation agent for the damage recovery process cannot enter theinside of the Low-k film, so the damage recovery is limited to a certaindegree.

On the other hand, even under the same process conditions, where no RFpower is applied to the second RF power supply 260, the resist film isprocessed predominantly by oxygen radicals contained in plasma.Consequently, the Low-k film is less damaged by oxygen ions, so thesurface structure of the Low-k film is prevented from becoming denser.On the other hand, since the Low-k film is not dense, the Low-k film isinternally more influenced by oxygen radicals, and thus may be moredamaged at a deeper side. However, the silylation agent can enter deeplyinside the Low-k film, so the damage there can be recovered.

Table 4 shows results of an experiment in removing a resist film byoxygen radicals. As regards Table 4, Sample 31 was set as a reference.Sample 32 was prepared by subjecting the reference to an ashing process.The conditions of the ashing process were the same as those for Sample21 shown in Table 3 except for no RF being applied to the second RFpower supply 260. Sample 33 was prepared by performing a recoveryprocess using a silylation agent after the ashing process. Sample 34 wasprepared by performing a resist film removing process using oxygenradicals, a cleaning process, and the recovery process using thesilylation agent, in this order.

As shown in Table 4, after the resist film was removed by oxygenradicals, the specific dielectric constant was increased. However, afterthe recovery process using the silylation agent was performed, thespecific dielectric constant was greatly recovered. Further, where theresist film removing process, cleaning process, and recovery processusing the silylation agent were performed in this order, the specificdielectric constant was recovered to a level essentially equal to thatof Sample 31 used as a reference. This is thought to have been attained,because moisture necessary for the silylation reaction was supplied bythe cleaning process, and the recovery process was thereby promoted.Further, a dense layer may have been formed in the surface of the Low-kfilm during the etching process, as in the ashing process, as describedabove. However, it is thought that this dense layer was removed by thecleaning process, and the recovery process was thereby promoted.

TABLE 4 Specific Recovery Sample dielectric rate No. Process conditionsconstant (%) 31 Reference 2.45 — 32 Resist film removal by 3.35 — oxygenradicals 33 Resist film removal by 2.69 74 oxygen radicals + Silylationprocess 34 Resist film removal by 2.54 97 oxygen radicals + Cleaningprocess + Silylation process

Also in a case where the resist film is removed by oxygen radicals, thefollowing procedures may be employed, as in the embodiment using O₂ gasplasma described above. Specifically, before the silylation process,atmospheric gas is supplied into the chamber 301, and then a pre-bakingis performed to adjust moisture amount to promote the silylationreaction. Further, in order to promote the silylation reaction, thewafer may be heated also after starting supply of the silylation agentto a temperature higher than that of the pre-baking.

In the second embodiment, the apparatus shown in FIG. 16 as an ashingunit 153 may serve as an apparatus for performing two or all of theetching process, ashing process, and recovery process. Specifically, forexample, where the process gas supply source 240 is arranged to supplyan etching process gas and an ashing process gas, the etching processgas is first supplied to perform the etching process, and then isswitched to the ashing process gas to perform the ashing process.Alternatively, where the process gas supply source 240 is arranged tosupply an etching process gas, an ashing process gas, and a silylationagent, the etching process gas is first supplied to perform the etchingprocess, then is switched to the ashing process gas to perform theashing process, and then is switched to the silylation agent to performthe silylation process. However, where the silylation process isperformed, it is necessary to dispose means for supplying moisture ontothe wafer W.

In the etching/ashing/recovering apparatus 108, before the silylationprocess, atmospheric gas is supplied into the silylation unit (SCH) 154.Alternatively, atmospheric gas may be supplied into another unit, suchas the wafer transfer chamber 155, to apply moisture onto the wafer. Asmeans for supplying moisture, a substance other than atmospheric gas,such as refined water vapor, may be supplied.

The present invention is not limited to the embodiments described above,and it may be modified in various manners. For example, the recoveryprocess is exemplified by the silylation process, but the recoveryprocess may be performed using another recovery gas. The etching targetfilm to which the present invention is applied is preferably a Low-kfilm, as described above, such as a porous MSQ (Porousmethyl-hydrogen-SilsesQuioxane) formed by an SOD apparatus.Alternatively, for example, an SiOC-based film, which is an inorganicinsulating film formed by CVD, may be used. This film can be preparedfrom a conventional SiO₂ film by introducing methyl groups (—CH₃) intoSi—O bonds present on the film to mix Si—CH₃ bonds therewith. BlackDiamond (Applied Materials Ltd.), Coral (Novellus Ltd.), and Aurora (ASMLtd.) correspond to this type. Some of them are dense while others areporous (with a lot of pores). However, the etching target film is notlimited to a Low-k film.

In the embodiments described above, the present invention is applied toa semiconductor device manufacturing process using a single damascenemethod or dual damascene method to form a copper interconnection line,but this is not limiting. The present invention may be applied to anysemiconductor device manufacturing process which includes a step ofremoving an etching mask on an etching target film.

Furthermore, the present invention should be construed to encompassarrangements obtained by suitably combining some of the components ofthe embodiments described above or excluding some of the components ofthe embodiments described above, as long as they do not depart from thespirit or scope of the present invention.

1. A substrate processing system for processing a target object preparedby forming an etching mask having a predetermined circuit pattern on asurface of an etching target film disposed on a semiconductor substrate,and then etching the etching target film through the etching mask toform a groove or hole in the etching target film, the system comprising:a denaturing apparatus that denatures the etching mask, by use of aprocess gas containing ozone and water vapor, to be soluble in apredetermined liquid containing purified water or a chemical solution; acleaning apparatus that dissolves and removes the etching mask thusdenatured by use of the predetermined liquid; a recovering apparatusthat recovers damage of the etching target film by use of apredetermined recovery gas; and a control section that controls anoperation of the system, the control section including a computerreadable non-transitory storage medium that stores a control program,which, when executed, controls the system to conduct a sequenceincluding removing the etching mask by denaturing the etching mask byuse of the process gas in the denaturing apparatus, and then dissolvingthe etching mask thus denatured by use of the predetermined liquid inthe cleaning apparatus, and then recovering damage of the etching targetfilm, caused before or in said removing the etching mask, by use of thepredetermined recovery gas in the recovering apparatus, wherein saidrecovering damage includes heating the semiconductor substrate at afirst temperature without supplying a silylation gas onto thesemiconductor substrate to remove moisture remaining on thesemiconductor substrate, and then supplying the silylation gas as therecovery gas onto the semiconductor substrate to recover the damage by asilylation process.
 2. The system according to claim 1, wherein thedenaturing apparatus, the cleaning apparatus, and the recoveringapparatus are arranged in the same unit.
 3. The system according toclaim 1, wherein said recovering damage includes heating thesemiconductor substrate at a second temperature higher than the firsttemperature along with said supplying the silylation gas to recover thedamage by the silylation process.
 4. The system according to claim 3,wherein the second temperature falls within a range of 50 to 150° C. 5.The system according to claim 1, wherein the sequence further includescleaning the semiconductor substrate after said removing the etchingmask and before said recovering damage.
 6. The system according to claim1, wherein the silylation gas contains a compound including silazanebonds (Si—N) in molecules.
 7. The system according to claim 6, whereinthe compound is selected from the group consisting of TMDS(1,1,3,3-Tetramethyldisilazane), TMSDMA (Dimethylaminotrimethylsilane),DMSDMA (Dimethylsilyldimethylamine), TMSPyrole (1-Trimethylsilylpyrole),BSTFA (N,O-Bis(trimethylsilyl)trifluoroacetamide), and BDMADMS(Bis(dimethylamino)dimethylsilane).
 8. A computer readablenon-transitory storage medium that stores a control program to control asubstrate processing system for processing a target object prepared byforming an etching mask having a predetermined circuit pattern on asurface of an etching target film disposed on a semiconductor substrate,and then etching the etching target film through the etching mask toform a groove or hole in the etching target film, the system including adenaturing apparatus that denatures the etching mask, by use of aprocess gas containing ozone and water vapor, to be soluble in apredetermined liquid containing purified water or a chemical solution, acleaning apparatus that dissolves and removes the etching mask thusdenatured by use of the predetermined liquid, and a recovering apparatusthat recovers damage of the etching target film by use of apredetermined recovery gas, the control program, when executed,controlling the system to conduct a sequence including removing theetching mask by denaturing the etching mask by use of the process gas inthe denaturing apparatus, and then dissolving the etching mask thusdenatured by use of the predetermined liquid in the cleaning apparatus,and then recovering damage of the etching target film, caused before orin said removing the etching mask, by use of the predetermined recoverygas in the recovering apparatus, wherein said recovering damage includesheating the semiconductor substrate at a first temperature withoutsupplying a silylation gas onto the semiconductor substrate to removemoisture remaining on the semiconductor substrate, and then supplyingthe silylation gas as the recovery gas onto the semiconductor substrateto recover the damage by a silylation process.
 9. The storage mediumaccording to claim 8, wherein said recovering damage includes heatingthe semiconductor substrate at a second temperature higher than thefirst temperature along with said supplying the silylation gas torecover the damage by the silylation process.
 10. The storage mediumaccording to claim 9, wherein the second temperature falls within arange of 50 to 150° C.
 11. The storage medium according to claim 8,wherein the sequence further includes cleaning the semiconductorsubstrate after said removing the etching mask and before saidrecovering damage.
 12. The storage medium according to claim 8, whereinthe silylation gas contains a compound including silazane bonds (Si—N)in molecules.
 13. The storage medium according to claim 12, wherein thecompound is selected from the group consisting of TMDS(1,1,3,3-Tetramethyldisilazane), TMSDMA (Dimethylaminotrimethylsilane),DMSDMA (Dimethylsilyldimethylamine), TMSPyrole (1-Trimethylsilylpyrole),BSTFA (N,O-Bis(trimethylsilyl)trifluoroacetamide), and BDMADMS(Bis(dimethylamino)dimethylsilane).